This invention relates to semiconductor devices and more specifically, relates to a novel structure for such a device in which an array of planar cells are formed in a single silicon wafer and are dielectrically isolated from one another and in which one or more power devices can be integrated into the same chip as the planar cells.
It is often desirable to utilize a semiconductor device formed of a large number of cells. Photovoltaic generators (PVGs), for example, are well known and are commonly used for producing a control signal for a solid state relay. Such devices employ an LED which is energized by input terminals to irradiate the photosensitive surface of a spaced and insulated photovoltaic device. The output of the photovoltaic device may serve as the input to a switching device, such as a MOS-gated device, typically a power MOSFET or IGBT, which has load terminals which are switched xe2x80x9conxe2x80x9d in response to the energization of the LED. The input and output terminals of the relay are isolated by the gap between the LED and the photovoltaic device. Commonly, the photovoltaic device consists of a large number of series-connected photovoltaic cells in order to produce a voltage sufficiently high to turn on the power switching device. Such devices are well known and are sold under the name xe2x80x9cPVIxe2x80x9d (photovoltaic isolator) by the International Rectifier Corporation of El Segundo, Calif., the assignee of the present invention.
The plural cell photogenerator can be made in many different ways. One known generator employs a stack or pile of photovoltaic cells as shown in U.S. Pat. Nos. 4,755,697 and 4,996,577, both to Daniel M. Kinzer. Other devices employ a planar array of cells which are junction isolated from one another and are connected in series at their surfaces. Still other devices are known in which individual cells disposed over the surface of a silicon chip are junction-isolated from one another or may be dielectrically isolated, as shown in U.S. Pat. Nos. 4,227,098 and 4,390,790. The prior art devices, however, have the drawback of being expensive to manufacture as well as having low manufacturing yields.
Alternatively, a planar array of photovoltaic generating cells are formed in a dielectrically bonded silicon wafer. A relatively thick xe2x80x9chandlexe2x80x9d wafer is oxide bonded to, as well as insulated from, a thin device wafer in which the junctions are formed, as shown in U.S. Pat. No. 5,549,762 to the present applicant. This device, however, requires a relatively expensive starting wafer.
It is therefore desirable to produce a photovoltaic generator that can be formed of a large number of insulated cells which can be connected in series to produce a turn-on signal for a power MOS-gated device but which is easily manufactured and integrated with the MOS-gated device using existing reliable processing equipment and techniques.
It is also desirable to produce other devices that can be formed of a large number of insulated cells which can be connected but which are easily manufactured and integrated with other devices.
The present invention provides a novel device structure which includes a trench structure that is used to dielectrically isolate the respective cells of a multiple cell semiconductor device formed in a single wafer.
One or more N+ or P+ diffusions may be first formed in a lightly doped P or N type starting wafer. Alternatively, these diffusions can be formed after the trench processing is completed. Individual planar and spaced cells or tubs are then formed by etching an array of intersecting trenches which surround the diffusions. The trenches extend to a predefined depth and are filled with a dielectric and with polysilicon to dielectrically insulate each of, the cells. The diffusions of the various cells are connected to one or more diffusions of an adjacent cell to connect a predetermined number of the cells in series or in parallel.
The back side of the silicon is then ground off at least to the level of the bottom of the trenches, and an insulating oxide may be deposited on the back surface. A beam support may be used to insure that the trenched, ground wafer holds together.
In accordance with the present invention, dielectrically isolated, planar photovoltaic generating cells may be formed in a single wafer and, furthermore, may be integrated with one or more power devices in the same wafer.
A plurality of N+ (or P+) diffusions are formed in a lightly doped P type (or N type) starting wafer and are each enclosed by a ring shaped P+ (or N+) contact diffusion. Note that these diffusions can be made at the end of the process. Individual planar and spaced cells or tubs are then formed by etching an array of intersecting trenches between the P+ (or N+) contact diffusions. The trenches extend to a predefined depth and are then filled with a dielectric and with polysilicon. The substrate is then thinned to dielectrically insulate each of the tubs. The N+ top contact of each cell is connected to the P+ contact of an adjacent cell to connect each of a predetermined number of the cells in series.
An MOS-gated device may be integrated into the same chip as the photovoltaic generator structure in a trenched or an untrenched area of the wafer. The MOS-gated device, which may a lateral or vertical MOSFET or a lateral or vertical IGBT, is formed prior to the grinding of the back side of the wafer and may be formed prior to or subsequent to the formation of the photovoltaic generator cells or may be formed by some processing steps that are common with those of the photovoltaic generator cells.
The upper surface of the device is then exposed to light, such as the radiation output of a spaced LED, to produce output voltages from each of the cells. These outputs, which are connected in series, produce a signal which can control the switching of the MOS-gated device.
In accordance with a further aspect of the invention, significantly, other devices can be integrated into other dielectrically isolated cells of the wafer. For example, MOS-gated devices such as BJTS, MOSFETs, IGBTs, GTDs and the like can be formed in other isolated cells of the common wafer. Contact circuits can also be integrated in other isolated wells. The devices integrated in other wells can be lateral conduction devices, or even vertical conduction devices in which the cells containing vertical conduction devices will also contain a bottom contact. Significantly, the entire wafer can be used with all cells containing various circuit components to be interconnected to form a particular circuit.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.